The integration of a large number of components on a single integrated circuit (IC) chip requires complex interconnects. Ideally, the interconnect structures should be fabricated with minimal signal delay and optimal packing density. The reliability and performance of integrated circuits may be affected by the qualities of their interconnect structures.
Advanced multiple metallization layers have been used to accommodate higher packing densities as devices shrink below sub-0.25 micron design rules. One such metallization scheme is a dual damascene structure formed by a dual damascene process. The dual damascene process is a two-step sequential mask/etch process to form a two-level structure, such as a via connected to a metal line situated above the via.
As illustrated in FIG. 1, a known dual damascene process begins with the deposition of a first insulating layer 14 over a first level interconnect metal layer 12, which in turn is formed over or within a semiconductor substrate 10. A second insulating layer 16 is next formed over the first insulating layer 14. An etch stop layer 15 is typically formed between the first and second insulating layers 14, 16. The second insulating layer 16 is patterned by photolithography with a first mask (not shown) to form a trench 17 corresponding to a metal line of a second level interconnect. The etch stop layer 15 prevents the upper level trench pattern 17 from being etched through to the first insulating layer 14.
As illustrated in FIG. 2, a second masking step followed by an etch step are applied to form a via 18 through the etch stop layer 15 and the first insulating layer 14. After the etching is completed, both the trench 17 and the via 18 are filled with metal 20, which is typically copper (Cu), to form a damascene structure 25, as illustrated in FIG. 3. If desired, a second etch stop layer, such as stop layer 29 of FIG. 4, may be formed between the substrate 10 and the first insulating layer 14 during the formation of a dual damascene structure 26.
Damascene processes such as the ones described above pose significant problems. One of the problems is caused by the use of one or more etch stop layers. The etch stop layers 15, 29 prevent the damascene patterns 17, 18 from extending into or through the underlying layers 14, 10. Although the advantages of using the etch stop layers are significant, the process is complex since separate depositions are required for the etch stop layers.
In addition, the most commonly used etch stop material, silicon nitride (Si3N4), has a rather high dielectric constant (k) (approximately 7), which does not satisfy anymore the requirement of resistance-capacitance delay regarding the parasitic capacitance generated by an intermetal insulating layer. As integrated circuits become denser, it is increasingly important to minimize stray capacitance between the metal layers. This is accomplished by using intermetal insulating layers that have a low dielectric constant, such as, for example, organic dielectric materials. Silicon nitride does not satisfy the requirement of small stray capacitance of advanced damascene structures.
Accordingly, there is a need for an improved damascene process which reduces production costs and increases productivity. There is also a need for a damascene process that does not require etch stop layers, as well as a method for decreasing the stray capacitance between the metal layers of damascene structures.